DACs are common in modern integrated circuits, particularly in switched capacitor CMOS designs. They have uses in many applications, including analog-to-digital converters (ADC) architectures such as pipelined and successive approximation (SAR) ADCs. Depending on the application, key performance metrics can be the DAC settling speed and settling time. Settling is a phenomenon that arises in DACs, such as charge redistribution, current and resistor-ladder. When a DAC is set to a new configuration, an output voltage may fluctuate due to various reasons for an indeterminate amount of time before arriving at a reliable value. The output voltage should not be processed by other system components until it completes settling and, therefore, settling speeds limit overall throughput of the DAC.
A conventional 3-bit charge redistribution DAC 100 is shown in FIG. 1. It is composed of binary-weighted capacitors 102, 104.1, 104.2 and 104.3 with respective capacitances of 1C, 1C, 2C and 4C. The DAC input is a 3 bit binary digital word with each bit controlling a respective switch of the switches 106.1, 106.2 and 106.3 connected to the capacitors. The other side of the switches 106.1, 106.2 and 106.3 goes to a reference voltage VREF or ground GND depending on the corresponding bit of the DAC input word. Typically, a digital “1” controls a corresponding switch to connect to the reference voltage VREF and a digital “0” controls a corresponding switch to connect to ground GND. The DAC output is determined by an equation of Vout=VREF*Cselected/Ctotal, in which Cselected is the amount of capacitance selected by the DAC word, and Ctotal is the sum of all the capacitance. For example, if the DAC code is 101, the capacitors 104.1 and 104.3 are selected by connecting the switches 106.1 and 106.3 to the reference voltage VREF, and the switch 106.2 connects the capacitor 104.2 to the ground GND. The output would be Vout=VREF*(4C+1C)/(4C+2C+1C+1C)=⅝*VREF. However, the DAC may not settle on an output Vout immediately in response to digital logic. Therefore, some time has to be allocated to allow the DAC to settle to an appropriate output voltage Vout for each respective digital code word to be converted.
In a typical switched capacitor (charge redistribution) digital-to-analog converter (DAC), the operation of the DAC may be affected by a number of conditions. For example, a DAC may operate faster at lower temperatures, or when a high supply voltage is applied. Another condition that may affect DAC operation may be fabrication processes (such as slow or fast corners). By allocating a fixed DAC time during bit trials for the DAC to settle to a value (i.e., settling time), the worst case conditions have to be considered (e.g., slow corner from the fabrication process, low supply voltage and high temperature, or, in general, process, voltage and temperature (PVT) variations). In addition, no matter the number of bits that a DAC is designed to convert, the most significant bit (MSB), typically, requires the greatest amount of time to convert. Therefore, the fixed DAC time must account for these conditions, if a desired level of accuracy is to be attained. As a result, the fixed DAC time is set for these worst case conditions, and is used inefficiently when the worst case conditions do not occur. For example, the DAC may complete its operation, settled to a output value, and remain in substantially a steady state as the fixed time clock times out. Similarly, the other components forming the ADC may have also completed processing and may be standing idle also waiting for the conversion result from the DAC. It would be beneficial if the DAC could indicate when it completed converting the input signal (i.e., settled to an output value), and allow the DAC to operate according to its operating conditions instead of a fixed time period.
The inventor has recognized a solution to the above problem and has developed a method and a device for realizing the above described benefits. As a result, part of the DAC settling time may be saved, and be allocated to other components of the signal supply chain, all of which may result in lower overall power consumption, and improved noise performance of the DAC and related devices.